1. Field of the Invention
The present invention relates to a manufacturing method of a semiconductor device. More particularly, it relates to a manufacturing method of MOS transistors having LDD (Lightly Doped Drain) structure.
2. Prior Art
The LDD structure, which is used as a measure to prevent high pressure resistance of MOS transistors and hot carriers, was a primary feature in sub-micron generation technology although, with the increasingly thinner gate oxide films in recent half-micron generation technology, it has become clear that degradation of the resistance due to hot carriers occurs even if a LDD structure is used.
A gate overlap type transistor has been proposed as a transistor to improve hot carrier resistance. Continuous oblique rotating ion implantation is used as a method to form the gate overlap type transistor (Semiconductor World 1990, 3, pp. 122 to 128). This method, however, is not suited for mass production.
Furthermore, a transistor with a structure using an inverse T-type gate has also been proposed (Japanese Patent Unexamined Publication JPA 3-88338 (1991)) although the film quality of the gate of the overlap portion is poor due to the fact that the film is exposed to an etchant. When the capacity of the overlap portion is applied to the gate in a transistor utilizing this structure, a problem occurs in which the speed is reduced due to the above shortcoming.
In order to improve the above problem, a method to increase the film thickness of the overlap portion has been proposed (Japanese Patent Unexamined Publication JPA 5-133435 (1993)). This manufacturing method illustrated in FIG. 3 (a) to FIG. 3 (f) will be explained below using a N-channel type transistor as an example.
(a) Using an ordinary method (for example, LOCOS method "Local Oxidation of Silicon") to form an element separation region 41 comprising an oxide film and then oxidizing the entire surface, a gate oxide film 43 forms in the active region 42 between the element separation regions 41. Then, polysilicon and a SiN film 44 are continuously grown on the entire surface, thereafter patterning is carried out in a prescribed pattern to form a gate electrode 45 (see FIG. 3 (a)).
(b) Oxidizing the entire surface, silicon oxide layer 46 forms on top of the gate oxide film 43 which is exposed and on the side of the gate electrode 45 (see FIG. 3 (b)).
(c) Ion impurities are implanted through the silicon oxide layer 46 on top of the active region 42 on the surface layer of the substrate (see FIG. 3 (c)).
(d) By growing polysilicon on the entire surface and carrying out anisotropic etching, a sidewall spacer 47 forms, which comprises polysilicon on the sidewalls of the gate electrode 45 through the silicon oxide layer 46 (see FIG. 3 (d)).
(e) Ion impurities are implanted through the silicon oxide layer 46 on top of the active region 42 on the surface layer of the substrate (see FIG. 3 (e)).
(f) The SiN film 44 on the top of the gate electrode 45 is removed. Then, a film is formed by sputtering Ti on the entire surface and, an annealing process at a prescribed temperature forms a TiSi2 film 48 on top of the gate electrode 45 and on the exposed surface of the sidewall spacer 47. Next, by selectively removing Ti formed on the oxide film, a gate overlap type transistor can be manufactured without using continuous oblique rotating ion implantation (see FIG. 3 (f)). Further, the TiSi2 film 48 functions as a silicide strap for the electrical connection between the gate electrode 45 and the sidewall spacer 47.
In the gate overlap type transistor shown in FIG. 3 (a) to (f) above, the selectivity between the gate oxide film 43 and the polysilicon must be very large while patterning the gate electrode 45. When this selectivity cannot be made large, the gate oxide film 43 will be removed simultaneously while patterning the gate electrode 45, damaging the substrate below the edge of the gate electrode 45.
The oxidation treatment (see FIG. 3 (b)) after the gate electrode 45 is formed oxidizes the edge of the gate electrode 45, thus causing jumping 49 to occur (see FIG. 4). This jumping 49 is the reason that the transistor characteristics such as their current drive capabilities are markedly reduced. Furthermore, when the sidewall spacer 47 is electrically connected to the gate electrode 45, a silicide strap must be provided, thereby increasing the number of processes.